// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  hipciec_ap_iob_rx_am_reg_reg_offset.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2017/10/24
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/16 18:03:15 Create file
// ******************************************************************************

#ifndef __HIPCIEC_AP_IOB_RX_AM_REG_REG_OFFSET_H__
#define __HIPCIEC_AP_IOB_RX_AM_REG_REG_OFFSET_H__

/* HIPCIEC_AP_IOB_RX_AM_REG Base address of Module's Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE                       (0x6000)

/******************************************************************************/
/*                      HiPCIECTRL40V200 HIPCIEC_AP_IOB_RX_AM_REG Registers' Definitions                            */
/******************************************************************************/

#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_GLOBAL_CTRL_0_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x0)   /* AXIM global control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_GLOBAL_CTRL_1_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x100) /* AXIM global control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_GLOBAL_CTRL_2_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x200) /* AXIM global control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_MAX_TRANS_CTRL_0_REG      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x4)   /* AXIM max outstanding number control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_MAX_TRANS_CTRL_1_REG      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x104) /* AXIM max outstanding number control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_MAX_TRANS_CTRL_2_REG      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x204) /* AXIM max outstanding number control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_QOS_CTRL_0_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x8)   /* AXIM qos control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_QOS_CTRL_1_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x108) /* AXIM qos control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_QOS_CTRL_2_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x208) /* AXIM qos control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_ARUSER_MODE_CTRL_0_REG    (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x20)  /* AXIM aruser control. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_ARUSER_MODE_CTRL_1_REG    (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x120) /* AXIM aruser control. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_ARUSER_MODE_CTRL_2_REG    (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x220) /* AXIM aruser control. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_ARUSER_SET_0_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x24)  /* AXIM aruser vaule set, index 0. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_ARUSER_SET_0_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x124) /* AXIM aruser vaule set, index 0. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_ARUSER_SET_0_2_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x224) /* AXIM aruser vaule set, index 0. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_ARUSER_SET_1_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x28)  /* AXIM aruser vaule set, index 1. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_ARUSER_SET_1_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x128) /* AXIM aruser vaule set, index 1. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_ARUSER_SET_1_2_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x228) /* AXIM aruser vaule set, index 1. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_ARUSER_SET_2_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x2C)  /* AXIM aruser value set, index 2. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_ARUSER_SET_2_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x12C) /* AXIM aruser value set, index 2. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_ARUSER_SET_2_2_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x22C) /* AXIM aruser value set, index 2. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_AWUSER_MODE_CTRL_0_REG    (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x30)  /* AXIM awuser control. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_AWUSER_MODE_CTRL_1_REG    (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x130) /* AXIM awuser control. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_AWUSER_MODE_CTRL_2_REG    (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x230) /* AXIM awuser control. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_AWUSER_SET_0_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x34)  /* AXIM awuser vaule set, index 0. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_AWUSER_SET_0_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x134) /* AXIM awuser vaule set, index 0. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_AWUSER_SET_0_2_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x234) /* AXIM awuser vaule set, index 0. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_AWUSER_SET_1_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x38)  /* AXIM awuser vaule set, index 1. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_AWUSER_SET_1_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x138) /* AXIM awuser vaule set, index 1. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_AWUSER_SET_1_2_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x238) /* AXIM awuser vaule set, index 1. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_AWUSER_SET_2_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x3C)  /* AXIM awuser value set, index 2. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_AWUSER_SET_2_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x13C) /* AXIM awuser value set, index 2. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_AXIM_AWUSER_SET_2_2_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x23C) /* AXIM awuser value set, index 2. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_MAX_TRANS_0_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x80)  /* AXIM max used outstanding number */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_MAX_TRANS_1_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x180) /* AXIM max used outstanding number */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_MAX_TRANS_2_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x280) /* AXIM max used outstanding number */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_DAT_STS_0_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x84)  /* AXIM data channel state */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_DAT_STS_1_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x184) /* AXIM data channel state */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_DAT_STS_2_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x284) /* AXIM data channel state */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_AXI_RESP_ERR_STS_0_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x88)  /* AXI response error state */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_AXI_RESP_ERR_STS_1_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x188) /* AXI response error state */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_AXI_RESP_ERR_STS_2_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x288) /* AXI response error state */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_AXI_GEN_REQ_0_REG          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x8C)  /* AXI Request state */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_AXI_GEN_REQ_1_REG          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x18C) /* AXI Request state */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_AXI_GEN_REQ_2_REG          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x28C) /* AXI Request state */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TXID_STS_0_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x90)  /* AXIM read transacion id state 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TXID_STS_0_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x190) /* AXIM read transacion id state 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TXID_STS_0_2_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x290) /* AXIM read transacion id state 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TXID_STS_1_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x94)  /* AXIM read transacion id state 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TXID_STS_1_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x194) /* AXIM read transacion id state 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TXID_STS_1_2_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x294) /* AXIM read transacion id state 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TXID_STS_2_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x98)  /* AXIM read transacion id state 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TXID_STS_2_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x198) /* AXIM read transacion id state 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TXID_STS_2_2_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x298) /* AXIM read transacion id state 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TXID_STS_3_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x9C)  /* AXIM read transacion id state 3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TXID_STS_3_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x19C) /* AXIM read transacion id state 3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TXID_STS_3_2_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x29C) /* AXIM read transacion id state 3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TXID_STS_0_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0xA0)  /* AXIM write transacion id state 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TXID_STS_0_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x1A0) /* AXIM write transacion id state 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TXID_STS_0_2_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x2A0) /* AXIM write transacion id state 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TXID_STS_1_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0xA4)  /* AXIM write transacion id state 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TXID_STS_1_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x1A4) /* AXIM write transacion id state 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TXID_STS_1_2_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x2A4) /* AXIM write transacion id state 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TXID_STS_2_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0xA8)  /* AXIM write transacion id state 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TXID_STS_2_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x1A8) /* AXIM write transacion id state 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TXID_STS_2_2_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x2A8) /* AXIM write transacion id state 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TXID_STS_3_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0xAC)  /* AXIM write transacion id state 3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TXID_STS_3_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x1AC) /* AXIM write transacion id state 3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TXID_STS_3_2_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x2AC) /* AXIM write transacion id state 3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RRESP_CONFLICT_STS_0_0_REG (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0xB0)  /* AXIM RRESP conflict state 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RRESP_CONFLICT_STS_0_1_REG (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x1B0) /* AXIM RRESP conflict state 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RRESP_CONFLICT_STS_0_2_REG (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x2B0) /* AXIM RRESP conflict state 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RRESP_CONFLICT_STS_1_0_REG (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0xB4)  /* AXIM RRESP conflict state 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RRESP_CONFLICT_STS_1_1_REG (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x1B4) /* AXIM RRESP conflict state 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RRESP_CONFLICT_STS_1_2_REG (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x2B4) /* AXIM RRESP conflict state 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RRESP_CONFLICT_STS_2_0_REG (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0xB8)  /* AXIM RRESP conflict state 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RRESP_CONFLICT_STS_2_1_REG (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x1B8) /* AXIM RRESP conflict state 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RRESP_CONFLICT_STS_2_2_REG (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x2B8) /* AXIM RRESP conflict state 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RRESP_CONFLICT_STS_3_0_REG (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0xBC)  /* AXIM RRESP conflict state 3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RRESP_CONFLICT_STS_3_1_REG (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x1BC) /* AXIM RRESP conflict state 3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RRESP_CONFLICT_STS_3_2_REG (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x2BC) /* AXIM RRESP conflict state 3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_BRESP_CONFLICT_STS_0_0_REG (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0xC0)  /* AXIM BRESP conflict state 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_BRESP_CONFLICT_STS_0_1_REG (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x1C0) /* AXIM BRESP conflict state 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_BRESP_CONFLICT_STS_0_2_REG (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x2C0) /* AXIM BRESP conflict state 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_BRESP_CONFLICT_STS_1_0_REG (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0xC4)  /* AXIM BRESP conflict state 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_BRESP_CONFLICT_STS_1_1_REG (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x1C4) /* AXIM BRESP conflict state 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_BRESP_CONFLICT_STS_1_2_REG (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x2C4) /* AXIM BRESP conflict state 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_BRESP_CONFLICT_STS_2_0_REG (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0xC8)  /* AXIM BRESP conflict state 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_BRESP_CONFLICT_STS_2_1_REG (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x1C8) /* AXIM BRESP conflict state 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_BRESP_CONFLICT_STS_2_2_REG (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x2C8) /* AXIM BRESP conflict state 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_BRESP_CONFLICT_STS_3_0_REG (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0xCC)  /* AXIM BRESP conflict state 3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_BRESP_CONFLICT_STS_3_1_REG (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x1CC) /* AXIM BRESP conflict state 3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_BRESP_CONFLICT_STS_3_2_REG (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x2CC) /* AXIM BRESP conflict state 3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_MEM_RD_LATENCY_0_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0xD0)  /* AXIM read latency */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_MEM_RD_LATENCY_1_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x1D0) /* AXIM read latency */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_MEM_RD_LATENCY_2_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x2D0) /* AXIM read latency */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_P2P_RD_LATENCY_0_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0xD4)  /* AXIM read latency */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_P2P_RD_LATENCY_1_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x1D4) /* AXIM read latency */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_P2P_RD_LATENCY_2_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x2D4) /* AXIM read latency */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_MEM_WR_LATENCY_0_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0xD8)  /* AXIM write latency */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_MEM_WR_LATENCY_1_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x1D8) /* AXIM write latency */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_MEM_WR_LATENCY_2_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x2D8) /* AXIM write latency */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_P2P_WR_LATENCY_0_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0xDC)  /* AXIM write latency */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_P2P_WR_LATENCY_1_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x1DC) /* AXIM write latency */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_P2P_WR_LATENCY_2_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x2DC) /* AXIM write latency */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_0_0_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0xE0)  /* Input NP TLP payload 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_0_1_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x1E0) /* Input NP TLP payload 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_0_2_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x2E0) /* Input NP TLP payload 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_1_0_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0xE4)  /* Input NP TLP payload 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_1_1_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x1E4) /* Input NP TLP payload 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_1_2_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x2E4) /* Input NP TLP payload 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_2_0_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0xE8)  /* Input NP TLP payload 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_2_1_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x1E8) /* Input NP TLP payload 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_2_2_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x2E8) /* Input NP TLP payload 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_3_0_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0xEC)  /* Input NP TLP payload 3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_3_1_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x1EC) /* Input NP TLP payload 3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_3_2_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x2EC) /* Input NP TLP payload 3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_0_0_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0xF0)  /* Input P TLP payload 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_0_1_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x1F0) /* Input P TLP payload 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_0_2_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x2F0) /* Input P TLP payload 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_1_0_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0xF4)  /* Input P TLP payload 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_1_1_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x1F4) /* Input P TLP payload 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_1_2_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x2F4) /* Input P TLP payload 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_2_0_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0xF8)  /* Input P TLP payload 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_2_1_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x1F8) /* Input P TLP payload 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_2_2_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x2F8) /* Input P TLP payload 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_3_0_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0xFC)  /* Input P TLP payload 3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_3_1_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x1FC) /* Input P TLP payload 3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_3_2_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_AM_REG_BASE + 0x2FC) /* Input P TLP payload 3 */

#endif // __HIPCIEC_AP_IOB_RX_AM_REG_REG_OFFSET_H__
